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[VHDL-FPGA-VerilogVerilog--Digital-Clock

Description: A digital Clock Implemented on Spartan-3, coded in Verilog... bit and ucf files have been attached along-with the source v-file- Will help a lot the students, beginners and hobbyists.
Platform: | Size: 10240 | Author: | Hits:

[Software EngineeringA-Verilog-HDL-Test-Bench-Primer

Description: 学习资料:详细说明了如何用Verilog语言编写Testbench文件-Learning materials: detailed description of how to use Verilog language Testbench file
Platform: | Size: 57344 | Author: | Hits:

[VHDL-FPGA-VerilogFPGA-Prototyping-By-Verilog-Examples

Description: <FPGA Prototyping By Verilog Examples>是Verilog指导性的书籍,这个压缩文件包含了PDF格式的电子书和书中的源代码,对于您的学习会有很大帮助。-<FPGA Prototyping By Verilog Examples> Verilog guidance books, The compressed file contains a PDF format e-books and the book' s source code, will be very helpful for your learning.
Platform: | Size: 17197056 | Author: 郑通 | Hits:

[VHDL-FPGA-Verilogdab1814114c3

Description: 此為採用ALTERA所做的DDR 控制器(verilog)- File/Directory Description ============================================================================= \doc DDR SDRAM reference design documentation \model Contains the verilog SDRAM model \route Contains the Quartus 2000.05 project files a routed controller design \simulation Contains the verilog testbench, modelsim project file, and library \source Contains the verilog source files for the DDR SDRAM reference design \synthesis\synplicity Contains all synplicity project files associated with synthesizing the reference design
Platform: | Size: 880640 | Author: 李志偉 | Hits:

[VHDL-FPGA-Verilogfir

Description: 16阶的FIR滤波器的verilog文件,包含了测试报告。-16 order FIR filter verilog file contains a test report.
Platform: | Size: 41984 | Author: luna | Hits:

[VHDL-FPGA-VerilogIR

Description: 是对9016遥控器解码的一个Verilog程序。-A verilog file about the decoding of 9016 remote-control unit.
Platform: | Size: 4248576 | Author: master | Hits:

[VHDL-FPGA-Verilogad9957-verilog

Description: 正交调制芯片,.v文件,但是没有说明文件,只能作为参考-Quadrature modulation chip,. V file, but no documentation, only as a reference
Platform: | Size: 2048 | Author: 张路平 | Hits:

[OtherVerilog---A-Guide-to-Digital-Design-and-Synthesis

Description: hdl file fir vlsi book
Platform: | Size: 9036800 | Author: som | Hits:

[VHDL-FPGA-VerilogVerilog-Accumulator

Description: the folder contains two files written by Verilog HDL. the first one is an implementation of an accumulator that takes serial data as an input, and its output will be an accumulated sum of each consecutive four input samples. the second file is a test bench for the first file to test its operation
Platform: | Size: 1024 | Author: sawsan | Hits:

[VHDL-FPGA-VerilogALU-and-Register-File

Description: ALU&Register Files(RF)之實現和其資料路徑的組合,包含了(1)ALU(2)Register File (RF)(3)Serial-in parallel-out register file(4)ALU + RF datapath-To learn the Verilog design for ALU and Register Files which are two main building blocks of a CPU.
Platform: | Size: 6144 | Author: sara kuo | Hits:

[VHDL-FPGA-Verilogfp24_prj

Description: 这是我利用Verilog编写的一个时钟计数器,包括了时钟分钟和秒,结构简单,功能细化,而且我也将仿真结果放在该压缩文件中,通过下载到FPGA的板子当中就可以实现计数,希望对初学FPGA的同学有帮助-This is what I use Verilog prepared a clock counter, including the clock minutes and seconds, simple structure, function refinement, and I will also be placed on the simulation results compressed file downloaded to the FPGA board through which you can achieve the count, I hope to help students beginner FPGA
Platform: | Size: 176128 | Author: 宗玥 | Hits:

[VHDL-FPGA-Verilogcruisecontrol.v

Description: This verilog file describes the design of a simple cruise controller employed in vehicles.
Platform: | Size: 1024 | Author: sinha.kaushik20 | Hits:

[VHDL-FPGA-Verilogvga789

Description: 这是一个Verilog的文件。可以实现在液晶显示屏山显示一副图像。-This is a Verilog file. Can display an image on the LCD Hill.
Platform: | Size: 5323776 | Author: lulei | Hits:

[Otherncd2verilog

Description: ncd文件转为verilog文件的脚本,包括perl脚本和netgen程序,双击实现转换,需要电脑可以运行perl脚本-ncd file into verilog file scripts, including scripts and perl netgen program, double achieve the conversion, you need a computer can run a perl script
Platform: | Size: 6144 | Author: yangzhao | Hits:

[VHDL-FPGA-Verilog08_counter_white

Description: verilog HDL 计数器 8位 计数值送数码管显示-this is a verilog file for counter
Platform: | Size: 3108864 | Author: 刘年 | Hits:

[VHDL-FPGA-Verilog02_buzzer

Description: verilog HDL 驱动蜂鸣器 驱动频率可调 驱动频率在1KHz时 无源蜂鸣器声音较大-this is a verilog file to driver the buzzer
Platform: | Size: 3134464 | Author: 刘年 | Hits:

[VHDL-FPGA-Verilogfsk_two

Description: FSK是数字调制中最为常见的一种调制方式 Verilog 文件可以在FPGA上完成实现功能。-FSK is a digital modulation in the most common form of modulation can be done to achieve functional Verilog file on the FPGA.
Platform: | Size: 1024 | Author: 陆从乐 | Hits:

[VHDL-FPGA-VerilogVerilog-HDL

Description: 此压缩文件包里是一些很经典的用Verilog硬件描述语言编写的程序,有需要的朋友可以看看。-This compressed file package is very classic with Verilog hardware description language programs, there is a need friends can see.
Platform: | Size: 114688 | Author: 西北野狼 | Hits:

[VHDL-FPGA-VerilogDDS-verilog

Description: DDS是直接数字式频率合成器(Direct Digital Synthesizer)的英文缩写,是一项关键的数字化技术。与传统的频率合成器相比,DDS具有低成本、低功耗、高分辨率和快速转换时间等优点,广泛使用在电信与电子仪器领域,是实现设备全数字化的一个关键技术。文件写了一个DDS的例程,并编写了TB文件。-DDS is a direct digital synthesizer (Direct Digital Synthesizer) of the English abbreviation, is a key digital technology. Compared with the traditional frequency synthesizer, DDS has the advantages of low cost, low power consumption, high resolution and fast conversion time. It is widely used in the field of telecommunication and electronic instrument, which is a key technology to realize the whole digitization of equipment. The file was written with a DDS routine and a TB file was written.
Platform: | Size: 2048 | Author: 林威 | Hits:

[VHDL-FPGA-Verilogip核

Description: 购买的beckoff公司的ip核,提供了详细的datasheet以及协议说明,附上调用ip核的文件,采用verilog编写,平台可以在ISE里自己设置(Buy the beckoff company's ip kernel, provides a detailed datasheet and protocol description, attached to the ip kernel file, using verilog prepared, the platform can be set in the ISE itself)
Platform: | Size: 4682752 | Author: cy白菜 | Hits:
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